Versal ACAP-Based Designs - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

To create the example design for Versal™ ACAPs:

1. In Vivado®, create a new block design in IP integrator.

2. Add the CPRI IP core to the canvas.

3. Select the CPRI IP core and configure as required.

4. Right-click the CPRI IP and select Open IP Example Design , from the drop-down menu as shown in the following figure. This opens a new Vivado project containing the complete design example.

Figure 6-1: Opening the Example Design for Versal ACAPs

X-Ref Target - Figure 6-1


The example design contains a loopback CPRI IP core connected to a Versal ACAP Transceiver and consists of the following:

An instance of the CPRI IP core.

A Versal ACAP GT Quad IP core.

An example VHDL wrapper containing data generators and checkers.

The example design can be run through the Vivado Implementation flow.

Note: The example design is not intended to be programmed onto a device as there are no device specific pin location constraints included in the example design xdc file.

Figure 6-2: CPRI Example Design for Versal ACAP Cores

X-Ref Target - Figure 6-2


Data generators are provided to stimulate the transmit IQ, Ethernet, HDLC, ORI, and vendor-specific data interfaces. The data arriving at the receive interfaces is checked against the transmitted data in monitor blocks. Error counters are incremented when mismatches are detected. The operation of the CPRI link can be tested by looping the serial output of the core back to the input and querying the status counters in the data monitors. Data generation and monitoring is enabled when the core is in the operational state.

The example design consists of the following VHDL source files:

<component_name>_example_design.vhd : Top-level example design encapsulating a CPRI core together with the data generator and monitor blocks. The example design instantiates the <component_name>_support.vhd file. This includes the CPRI encrypted RTL block along with the core and core support layers. It is expected that <component_name>.vhd is the block that designers instantiate in their design.

iq_tx_gen.vhd : IQ data generator. This block outputs a simple incrementing data pattern to the core transmit I/Q (Data) interface.

iq_rx_chk.vhd : IQ data monitor. This block checks the receive I/Q (Data) interface for the incrementing pattern output by the IQ data generator. Error and basic frame counters are provided.

mii_stim.vhd/gmii_stim.vhd : Ethernet data generator and monitor block. Dummy Ethernet frames are transmitted to the CPRI MII/GMII interface and the frames received are monitored. Transmit and receive frame counters are provided. An error counter is incremented when mismatches between the transmitted and received frames are detected.

hdlc_stim.vhd : The HDLC block sends a serial bit pattern generated by a pseudo-random binary sequence counter. The received pattern is checked for errors and a counter is incremented if any are detected.

vendor_stim.vhd : The vendor-specific block outputs words to the vendor-specific interface in sub channels 16 to 19. The words are generated by a pseudo-random binary sequence counter. The received pattern is checked for errors and a counter is incremented if any are detected.

ori_stim.vhd : An ORI stimulus block outputs and checks the port number and Ethernet MAC address of the core. In slave cores RTWP information is generated and in master cores the RTWP ports are monitored.