The following table shows the core transceiver interface when the core is generated without the core support layer.
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| Quad PLL Clock Ports | |||
| qpllclk_in | In | N/A | Output clock from the quad PLL QPLLOUTCLK port (AMD Kintex™ 7, AMD Virtex™ 7, AMD Zynq™ 7000 SoC only) |
| qpllrefclk_in | In | N/A | Output clock from the quad PLL QPLLOUTREFCLK port (Kintex 7, Virtex 7, Zynq 7000 SoC only) |
| qplllock_in | In | N/A | Cores supporting 9,830.4, 10,137.6 or 12,165.12 Mb/s only. Lock indication from the quad PLL. (Kintex 7, Virtex 7, Zynq 7000 SoC only) |
| qpll_pd | Out | Management Clock | Cores supporting 9,830.4, 10,137.6 or 12,165.12 Mb/s only. Asserted to power down the QPLL when it is not in use. (Kintex 7, Virtex 7, Zynq 7000 SoC only) |
| qpll0clk_in | In | N/A | Output clock from the quad PLL QPLL0OUTCLK port (UltraScale architecture-based devices only) |
| qpll0refclk_in | In | N/A | Output clock from the quad PLL QPLL0OUTREFCLK port (UltraScale architecture only) |
| qpll0lock_in | In | N/A | UltraScale architecture cores supporting 9,830.4, 10,137.6, 12,165.12, or 24,330.24 Mb/s only. Lock indication from QPLL0. |
| qpll0_pd | Out | Management Clock | UltraScale architecture cores supporting 9,830.4, 10,137.6, 12,165.12, or 24,330.24 Mb/s only. Asserted to power down QPLL0 when it is not in use. |
| qpll1clk_in | In | N/A | Output from the quad PLL QPLL1OUTCLK port (UltraScale architecture only) |
| qpll1refclk_in | In | N/A | Output from the quad PLL QPLL1OUTREFCLK port (UltraScale architecture only) |
| qpll1lock_in | In | N/A |
UltraScale architecture
supporting 9,830.4, 10,137.6, 12,165.12, or 24,330.24 Mb/s only. Lock indication from QPLL1. |
| qpll1_pd | Out | Management Clock |
UltraScale architecture cores
supporting 9,830.4, 10,137.6, 12,165.12, or 24,330.24 Mb/s only. Asserted to power down QPLL1 when not in use. |
| pll0clk_in | In | N/A | Output clock from the quad PLL PLL0OUTCLK port (Artix 7 only) |
| pll0refclk_in | In | N/A | Output clock from the quad PLL PLL0OUTREFCLK port (Artix 7 only) |
| pll0lock_in | In | N/A | Lock indicator from the quad PLL PLL0LOCK_OUT port (Artix 7 only) |
| pll1clk_in | In | N/A | Output clock from the quad PLL PLL1OUTCLK port (Artix 7 only) |
| pll1refclk_in | In | N/A | Output clock from the quad PLL PLL1OUTREFCLK port (Artix 7 only) |
| pll1lock_in | In | N/A | Lock indicator from the quad PLL PLL1LOCK_OUT port (Artix 7 only) |
| Alignment Interface | |||
| phase_alignment_ done_in | In | Async | Asserted High when phase alignment has completed |
| txdlysreset_in | In | Async | TX Delay Alignment Soft Reset |
| txdlysresetdone_out | Out | Management Clock | Asserted High to indicate that the TX delay alignment soft reset has completed |
| txphinit_in | In | Async | TX Phase Alignment initialization |
| txphinitdone_out | Out | Management Clock | Asserted High to indicate that TX phase alignment initialization has completed |
| txphalign_in | In | Async | Asserted High to set TX phase alignment |
| txphaligndone_out | Out | Management Clock | The second rising edge of the txphaligndone signal after txdlysresetdone assertion indicates that TX phase and delay alignment has completed |
| txdlyen_in | In | Async | Enables the TX delay alignment in manual mode |
When the core is generated with the core support layer option enabled, an illustration of how to connect the quad PLL and alignment interface signals for a single CPRI link is present in the <component_name>_support.vhd file. When the core is generated without the support layer this functionality is implemented in the example design.
The following table shows the transceiver interface when the core is generated with the core support layer option enabled. In this case, the output clocks from the GT common block are supplied to enable connection to three CPRI cores located in the same quad. The alignment interface signals are also extended to support sharing with up to three additional CPRI cores. The additional CPRI cores should be generated without the core support layer.
If the sharing of the GT common block is not
required, the Quad PLL ports can be left open. If alignment block sharing is not required
then the alignment interface ports should be looped back so that txdlysreset_out drives txdlysresetdone_in, txphinit_out drives txphinitdone_in and txphalign_out drives
txphaligndone_in. The phase_alignment_done_out and txdlyen_out ports
can be left open. See Resource Sharing for more information.
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| Quad PLL Clock Ports(1) | |||
| qpllclk_out | Out | N/A | Clock output from the GT common block in the core support layer (Kintex 7, Virtex 7, Zynq 7000 SoC only). |
| qpllrefclk_out | Out | N/A | Reference clock output from the GT common block in the core support layer (Kintex 7, Virtex 7, Zynq 7000 SoC only). |
| qplllock_out | Out | N/A | Cores supporting 9,830.4, 10,137.6, or 12,165.12 Mb/s only. Lock output from the GT common block in the core support layer. (Kintex 7, Virtex 7, Zynq 7000 SoC only). |
| qpll0clk_out | Out | N/A | QPLL0 clock output from the GT common block in the core support layer (UltraScale architecture only). |
| qpll0refclk_out | Out | N/A | QPLL0 reference clock output from the GT common block in the core support layer (UltraScale architecture only). |
| qpll0lock_out | Out | N/A | UltraScale architecture cores supporting 9,830.4, 10,137.6, 12,165.12, or 24,330.24 Mb/s only. QPLL0 lock output from the GT common block in the core support layer. |
| qpll1clk_out | Out | N/A | QPLL1 clock output from the GT common block in the core support layer (UltraScale architecture only). |
| qpll1refclk_out | Out | N/A | QPLL1 reference clock output from the GT common block in the core support layer (UltraScale architecture only). |
| qpll1lock_out | Out | N/A | UltraScale architecture cores supporting 9,830.4, 10,137.6, 12,165.12, or 24,330.24 Mb/s only. QPLL1 lock output from the GT common block in the core support layer. |
| pll0clk_out | Out | N/A | Clock output from PLL0 of the GT common block in the core support layer (Artix 7 only). |
| pll0refclk_out | Out | N/A | Reference clock output from PLL0 of the GT common block in the core support layer (Artix 7 only). |
| pll1clk_out | Out | N/A | Clock output from PLL1 of the GT common block in the core support layer (Artix 7 only). |
| pll1refclk_out | Out | N/A | Reference clock output from PLL1 of the GT common block in the core support layer (Artix 7 only). |
| Alignment Interface(2) | |||
| phase_alignment_done_out | Out | Async | Asserted High when the alignment block in the core support layer has completed TX phase alignment. |
| txdlysreset_out[2:0] | Out | Async | Signal from the alignment block resetting the TX delay alignment in the additional CPRI cores. |
| txdlysresetdone_in[2:0] | In | Async | The CPRI cores sharing the alignment block assert this signal when soft reset has been completed. |
| txphinit_out[2:0] | Out | Async | Signal from the alignment block initializing TX phase alignment in the additional CPRI cores. |
| txphinitdone_in[2:0] | In | Async | The CPRI cores sharing the alignment block assert this signal when phase alignment initialization has been completed. |
| txphalign_out[2:0] | Out | Async | Signal from the alignment block to set TX phase alignment in the additional CPRI cores. |
| txphaligndone_in[2:0] | In | Async | The CPRI cores sharing the alignment block assert this signal when TX phase alignment has been completed. |
| txdlyen_out[2:0] | Out | Async | Enables the TX delay alignment in manual mode. |
|
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For more information on the TX phase alignment process when the TX buffer is bypassed see the “TX Buffer Bypass” section in the UltraScale Architecture GTY Transceivers User Guide (UG578), the UltraScale Architecture GTH Transceivers User Guide (UG576), 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) and the 7 Series FPGAs GTP Transceivers User Guide (UG482).