| Bits | Description |
|---|---|
| 31:16 | Receiver Gearbox Latency |
| 15:0 | Transmitter Gearbox Latency |
This register is not used for Versal adaptive SoC. The gearbox latency values should be read directly from the Versal GT Quad through an AXI or APB3 interface. See the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).
In UltraScale-based cores operating at line rates of 8,110.08, 10,137.6, 12,165.12, and 24,330.24 Mb/s, the asynchronous gearbox is used to implement 64b66b encoding. The latency through the transmit and receive gearboxes is reported using this register.
See the UltraScale Architecture GTH Transceivers User Guide (UG576) and UltraScale Architecture GTY Transceivers User Guide (UG578) for more information on the asynchronous gearbox. The value is reported in units of 1/8 of a UI.