Delay Through the GTHE4 Transceiver - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

Delay through the GTHE4 transceiver consists of a variable component (barrel shift or TX and RX gearbox latency) and a fixed component. The fixed component is made up of the delay shown in the following table plus the additional line rate delay shown below.

Table 1. Fixed Contribution to Delay - GTHE4 Transceiver
Block Latency (UI)
TX 16-bit datapath cores (8b/10b) 85
32-bit datapath cores (8b/10b) 155
64-bit datapath cores (64b/66b) 176
RX 16-bit datapath cores (8b/10b) 134.5
32-bit datapath cores (8b/10b) 248.5
64-bit datapath cores (64b/66b) 125.5