The status interface can be connected to LEDs for easy debugging. It can also be connected to a general purpose Input/Output (I/O) of a management processor or another logic module, if required. The signals are all synchronous to aux_clk and are described in Table: Status Interface Signals .
|
Port |
Direction |
Clock Domain |
Description |
|---|---|---|---|
|
stat_alarm (1) |
Out |
Management
|
An alarm has been detected. It is set whenever any of the following conditions occur: • If the SDI bit or the Reset bit is set in the Transmit CPRI Alarms register • LOF, LOS, SDI, RAI, or Reset bit set in received Z.130.0 • Local LOF, LOS or RAI bits set |
|
stat_code[3:0] (1) |
Out |
Management
|
Current state of the core
0000 - Reset
|
|
Out |
Management
|
000 0000 0000 0000 - Core is disabled
|
|
|
reset_request_in |
In |
Management
|
Master cores only. When set High the core transmits a 1 in the reset bit of control word Z.130.0 of the outbound CPRI frame. This is identical to setting the reset bit High in the General Configuration and Transmit CPRI Alarms Register (0xE) register. When the master core is set to slave mode (core_is_master is Low) this pin functions as a reset acknowledge input. |
|
reset_acknowledge_in |
In |
Management
|
Slave cores only. When set High the core transmits a 1 in the reset bit of control word Z.130.0 of the outbound CPRI frame. This is identical to setting the reset bit High in the General Configuration and Transmit CPRI Alarms Register (0xE) register. |
|
sdi_request_in |
In |
Management
|
When set High the core transmits a 1 in the SDI bit of control word Z.130.0 of the outbound CPRI frame. This is identical to setting the SDI bit High in the General Configuration and Transmit CPRI Alarms Register (0xE) register. |
|
reset_request_out |
Out |
Management
|
Slave cores only. Holds the received value of the Reset bit in control word Z.130.0. |
|
reset_acknowledge_out |
Out |
Management
|
Master cores only. Holds the received value of the Reset bit in control word Z.130.0. When the master core is set to slave mode (core_is_master is Low) this pin functions as a reset request output. |
|
sdi_request_out |
Out |
Management
|
Holds the received value of the SDI bit in control word Z.130.0. |
|
local_los |
Out |
Management
|
Asserted if the core has detected loss of signal. |
|
local_lof |
Out |
Management
|
Asserted if the core has lost frame synchronization. |
|
local_rai |
Out |
Management
|
Asserted if the core has detected LOS or LOF. |
|
remote_los |
Out |
Management
|
Asserted if the core is receiving a LOS indication from the link partner in control word Z.130.0. |
|
remote_lof |
Out |
Management
|
Asserted if the core is receiving a LOF indication from the link partner in control word Z.130.0. |
|
remote_rai |
Out |
Management
|
Asserted if the core is receiving a RAI indication from the link partner in control word Z.130.0. |
|
fifo_transit_time (7) |
Out |
Management
|
FIFO Transit time value. This port mirrors the value held in the R21 Timers Register (0xF) register and High Resolution FIFO Transit Time registers (0x19) and (0x1A). This can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. |
|
fifo_transit_time_tx[13:0] |
Out |
Management
|
Transmit FIFO Transit time value. This port mirrors the value held in the Transmit FIFO transit time (0x14) register. This can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. Valid only for Zynq-7000 SoC, Kintex-7, and Virtex-7 based cores that support operation at 10,137.6 or 12,165.12 Mb/s. |
|
tx_gb_latency_value |
Out |
Management Clock |
Transmit gearbox latency. This port mirrors the value held in the lower 16-bits of the Gearbox Latency Register (0x16) register. Valid only for UltraScale architecture supporting 10,137.6, 12,165.12, or 24,330.24 Mb/s. Not valid for Versal ACAP. tx_gb_latency_value should be read directly from the Versal GT Quad through an AXI interface. |
|
rx_gb_latency_value |
Out |
Management Clock |
Receive gearbox latency. This port mirrors the value held in the upper 16-bits of the Gearbox Latency Register (0x16) register. Valid only for UltraScale architecture supporting 10,137.6, 12,165.12, or 24,330.24 Mb/s. Not valid for Versal ACAP. rx_gb_latency_value should be read directly from the Versal GT Quad through an AXI interface. |
|
coarse_timer_value[17:0] |
Out |
Management
|
Coarse timer value. This port mirrors the value held in the R21 Timers Register (0xF) register. This can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. |
|
barrel_shift_value[6:0] |
Out |
Management
|
Transceiver barrel shift position. This port mirrors the value held in the Transceiver Barrel Shift Position Register(0x9) register. This can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. Not valid for Versal ACAP. barrel_shift_value should be read directly from the Versal GT Quad through an AXI interface. |
|
stat_rx_delay_value |
Out |
Management Clock |
Fractional RX latency value. This port mirrors the value held in the FEC Status Register (0x1B) register. This can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. |
|
hyperframe_number |
Out |
Management Clock |
Gives the running count from 0-149 of the received hyperframe number. |
|
hfec_fifo_latency_value (15:0) |
Out |
Management Clock |
Variable latency through the Hard FEC. This port mirrors the value held in the Hard FEC Variable Latency register (0x20). This value can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. The value is the number of rx_fast_clk clock cycles. Multiply by 66 to get the latency in UI. |
|
Notes: 1. When the core is reset these signals do not update until the reset is deasserted.
2.
The width of stat_speed differs depending on the supported operating speed of the core as follows:
3. Not supported on -1 speed grade Artix-7 devices. 4. Not supported in Artix-7 devices, -1 speed grade in Virtex-7 and Kintex-7 devices and on -2/-3 speed grade Kintex-7 and Zynq-7000 SoC devices in non FFG packages. 5. This option is available on UltraScale architecture and on Virtex-7, Kintex-7, and Zynq-7000 SoC devices of speed grade -2 or -3 in FFG packages. 6. This option is available on UltraScale GTYE3 of speed grade -2 or -3, and UltraScale+ GTYE4 architecture-based devices of all speed grades.
7.
The width of fifo_transit_time varies depending on the selected CDC FIFO depth.
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