Feature Summary - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
Release Date
8.11 English

Designed to CPRI Specification v7.0 [Ref 1]

Can be configured as a master or slave at generation time. Master core can be switched to operate as a slave through a configuration port.

Suitable for use in both Radio Equipment Controllers (RECs) and Radio Equipment (RE), including multi-hop systems.

Easy-to-use interface for in-phase (I) and quadrature-phase (Q) data and synchronization together with optional modules for UMTS terrestrial radio access - frequency division duplexing (UTRA-FDD) and Evolved UMTS Terrestrial Radio Access (E-UTRA) data mappings. interface

Supports both Ethernet and HDLC Control and Management channels

Supports vendor-specific data transport including support for the passing of control AxC information in global system for mobile communications (GSM) systems

Includes the necessary clocking and transceiver logic to enable easy integration into your design

Synthesizable example design and simple demonstration test bench provided

Delay measurement capability meets CPRI Requirement 21 per CPRI Specification v7.0 [Ref 1]

Optional Reed-Solomon Forward Error Correction (RS-FEC) supported at 8,110.08 Mb/s, 10,137.6 Mb/s, 12,165.12 Mb/s, and 24,330.24 Mb/s line rates.

Optional 100G Ethernet RS-FEC supported at a line rate of either 24,330.24, 12,165.12, 10,137.6, or 8,110.08 Mb/s on selected UltraScale+ devices using GTYE4 transceivers. The Hard FEC can be shared with up to three further CPRI links.

CPRI core can be converted into a four lane Receiver Hard FEC IP, running at a fixed line rate of either 24,330.24, 12,165.12, 10,137.6, or 8,110.08 Mb/s (on UltraScale+ devices with 100G Ethernet RS-FEC support).

CPRI core can support Agnostic Line Coding Aware Mode for 9.8 Gb/s to 2.45 Gb/s in 8b10b and all 64b66b line rates in 64bit data width only. Soft FEC and Hard FEC options are also supported for 64b66b line rates.