HDLC Interface - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID

PG056

Release Date

2022-11-16

Version

8.11 English

The HDLC interface is also known as the Slow C&M Channel in the CPRI specification. When the CPRI link starts up, the default behavior is for the master and slave to negotiate a rate for the HDLC channel based on the highest common rate available to both ends of the link. The preferred rate for the CPRI core can be set through the management interface before link start-up. If the preferred rate is changed after the core is in operational mode, then negotiation restarts based on that new rate.

The ports of the HDLC interface are described in Table: HDLC Interface Port Signals .

Table 3-20: HDLC Interface Port Signals
Port	Direction	Clock Domain	Description
hdlc_tx_data	In	System Clock	HDLC serial data for transmission. Synchronous to clk.
hdlc_tx_enable	Out	System Clock	HDLC serial data transmit enable. Synchronous to clk.
hdlc_rx_data	Out	System Clock	Received HDLC serial data. Synchronous to clk.
hdlc_rx_data_valid	Out	System Clock	Data valid flag for received HDLC serial data. Synchronous to clk.

This Figure and This Figure show the HDLC interface timing when the HDLC Adaptation bit is set to 1 in the General Configuration and Transmit CPRI Alarms Register (0xE) management register. The transmit data port is a serial input synchronous to clk ( This Figure ); the receive data port is a serial port also synchronous to clk ( This Figure ). The CPRI core generates an enable for the transmit data port and a data valid signal for the receive data port at regular intervals. This maintains the average HDLC data rate negotiated at CPRI link start-up.

Figure 3-50: Transmit HDLC Interface Timing with HDLC Adaptation Bit Set to 1
X-Ref Target - Figure 3-50

X-Ref Target - Figure 3-51

Figure 3-51: Receive HDLC Interface Timing with HDLC Adaptation Bit Set to 1

This Figure and This Figure illustrate the HDLC interface timing when the HDLC Adaptation bit is set to zero in the General Configuration and Transmit CPRI Alarms Register (0xE) register. Here the CPRI core generates an enable that frames a burst of serial HDLC data. The data burst is the size of the speed related HDLC word. This is 2 bytes when the HDLC channel is operating at 240 kb/s, 4 bytes at 480 kb/s, 8 bytes at 960 kb/s, 16 bytes at 1,920 kb/s, and 20 bytes at 2,400 kb/s. The bursts are separated by half of a hyperframe at the lowest HDLC rate and by one quarter of a hyperframe at all other rates. This mode of operation is not supported in cores using a 32-bit or 64-bit datapath.

Figure 3-52: Transmit HDLC Interface Timing with HDLC Adaptation Bit Set to 0
X-Ref Target - Figure 3-52

Figure 3-53: Receive HDLC Interface Timing with HDLC Adaptation Bit Set to 0
X-Ref Target - Figure 3-53

If the current HDLC rate is set to the user-defined rate (111 in the Current HDLC Rate Register (0x2) management register) then the HDLC rate is negotiated on a higher layer. The HDLC byte valid vector in the Preferred HDLC Rate Register (0xA) management register can be used to set an HDLC rate that is not one of the pre-defined values given in Table: Current HDLC Rate Register . It should be noted that HDLC rate adaptation is not supported in this mode. In addition this mode of operation is not supported in devices using the 32-bit or 64-bit datapath.

Each bit in the 10-bit HDLC byte valid vector sets whether a particular byte in each of the HDLC words (Z.1, Z.65, Z.129 and Z.193) contains valid data. For example, if bit 0 in the HDLC byte valid vector is set to one, then byte 0 of each HDLC word contains valid data. The number of bytes in each HDLC word varies with line rate. Only the lowest n bits of the byte valid vector are valid at a particular speed, where n is the size of the word in bytes at that speed.

This Figure and This Figure illustrate the HDLC interface timing when the line rate is 3,072.0 Mb/s and the current HDLC rate is set to111. Here each HDLC word is 5 bytes wide. In this example the HDLC byte valid vector is set to 0000010101. The hdlc_tx_enable and hdlc_rx_data_valid signals are only set High on the first, third and fifth bytes of the HDLC serial data burst. This gives an HDLC bit rate of 1,440 kb/s.

Figure 3-54: Transmit HDLC Interface Timing with User Defined HDLC Rate
X-Ref Target - Figure 3-54

Figure 3-55: Receive HDLC Interface Timing with User Defined HDLC Rate
X-Ref Target - Figure 3-55

The CPRI core requires that the HDLC protocol be handled by an external controller that complies with the HDLC specification.