The ports in the following table added in
version 8.2 of the core. The qpll_select input is only
present for designs implemented in UltraScale architecture.
The clk_316_in port is only present on AMD Kintex™ 7, AMD Virtex™ 7 and AMD Zynq™ 7000-based designs supporting the 10,137.6 Mb/s line rate.
| Port | Direction | Upgrade Action |
|---|---|---|
| UltraScale Architecture Only | ||
| gtwiz_reset_clk_freerun_in | In | Drive with free running clock at less than the speed of the system clock at the lowest supported line rate. |
| Cores With Core Support Layer Only | ||
| gt_reset_req_out | Out | Leave open |
| UltraScale Architecture With Core Support Layer | ||
| qpll_select | In | Tie to 0 |
| qpll1clk_out | Out | Leave open |
| qpll1refclk_out | Out | Leave open |
| qpll1lock_out | Out | Leave open |
| UltraScale Architecture Without Core Support Layer | ||
| qpll_select | In | Tie to 0 |
| qpll1clk_in | In | Tie to 0 |
| qpll1refclk_in | In | Tie to 0 |
| qpll1lock_in | In | Tie to 0 |
| qpll1_pd | Out | Leave open |
| Cores Without Core Support Layer Supporting 10,137.6 Mb/s Only | ||
| clk_316_in | In | Tie to 0 |
| userclk_tx_reset | Out | Leave open |
| userclk_rx_reset | Out | Leave open |
| Transceiver Debug Ports (Kintex 7, Virtex 7, AMD Artix™ 7, AMD Zynq™ 7000 SoC) | ||
| gt0_drpdaddr_in[8:0] | In | Tie to 0 |
| gt0_drpdi_in[15:0] | In | Tie to 0 |
| gt0_drpen_in | In | Tie to 0 |
| gt0_drpwe_in | In | Tie to 0 |
| gt0_drpdo_out[15:0] | Out | Leave open |
| gt0_drprdy_out | Out | Leave open |
| Transceiver Debug Ports (UltraScale Architecture) | ||
| gt_drpdaddr[8:0] | In | Tie to 0 |
| gt_drpdi[15:0] | In | Tie to 0 |
| gt_drpen | In | Tie to 0 |
| gt_drpwe | In | Tie to 0 |
| gt_drpdo[15:0] | Out | Leave open |
| gt_drprdy | Out | Leave open |