Cores Supporting 10,137.6/12,165.12 Mb/s - 8.12 English - PG056

Zynq 7000 SoC, Virtex 7, and Kintex 7 devices

When running at 8,110.08, 10,137.6 or 12,165.12 Mb/s, the additional delay is 11 datapath clock cycles which equates to 363 UI. When running at lower speeds, the additional delay is 10 clock cycles, or 400 UI.

UltraScale architecture

The additional delay is nine datapath clock cycles when operating in 64B/66B mode and 8 datapath clock cycles otherwise. This equates to 297 UI when the core is operating at 10,137.6 and 320 UI at other speeds.