This chapter contains information about the test bench provided in the Vivado
®
Design Suite.
For information on setting up and running simulations in the Vivado Design Suite. See
Vivado Design Suite User Guide: Logic Simulation
(UG900)
[Ref 11]
. The CPRI™ LogiCORE
™
IP supports behavioral simulation along with post-implementation functional simulation.
This Figure
shows the structure of the CPRI test bench.
Figure 7-1:
CPRI Test Bench Structure
|
X-Ref Target - Figure 7-1
|
The CPRI test bench consists of:
•
An instantiation of the CPRI example, wired in serial loopback in the test bench. Loopback is not representative of a normal CPRI link.
•
Clock generation for the reference, management, Ethernet and high-speed clocks.
•
Global reset generation for the core.
•
A mu-Law encoder and decoder circuit as an example of an IQ compression technique.
The test bench monitors the status of the CPRI link and waits until the core enters the operational state. It waits until the IQ monitor has received 1,000 basic frames and then queries the frame and error counters in the data generator and monitor blocks.
A package file is included along with the test bench. This contains useful data types, constant definitions and functions to access the CPRI control and status registers (shown in
Table: Management Register Addresses
).
Table: Helper Functions Provided in Test Bench Package File
shows the helper functions available.
Table 7-1:
Helper Functions Provided in Test Bench Package File
|
Function
|
Description
|
|
read_rcvd_protocol_version
|
Returns the received protocol version from the Received Subchannel 2, Word 0 Register (0x4)
|
|
read_rcvd_seed
|
Returns the received seed from the Descrambler Seed Register (0x13)
|
|
read_rcvd_hdlc_rate
|
Returns the received HDLC rate from the Received Subchannel 2, Word 1 Register (0x5)
|
|
read_status_code
|
Returns the status code from the Status Code and Alarm Register (0x0)
|
|
read_status_alarm
|
Returns the summary alarm status from the Status Code and Alarm Register (0x0)
|
|
read_current_speed
|
Returns the negotiated line rate from the Current Line Speed Register (0xC)
|
|
read_tx_cpri_alarms
|
Returns the value of the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
read_reset
|
Returns the status of the reset bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
read_sdi
|
Returns the status of the SAP Defect Indicator bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
read_hdlc
|
Returns the negotiated HDLC rate from the Current HDLC Rate Register (0x2)
|
|
read_current_eth_ptr
|
Returns the value of the negotiated Ethernet pointer from the Current Ethernet Pointer Register (0x3)
|
|
write_speed_capability
|
Writes to the Line Speed Capability Register (0xD) to change the line rate on the link
|
|
write_set_sdi
|
Sets the SAP Defect Indicator bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
write_clear_sdi
|
Clears the SAP Defect Indicator bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
write_clear_hdlc_rate_adapt
|
Sets the HDLC rate adapt bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
write_set_hdlc_rate_adapt
|
Clears the HDLC rate adapt bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
write_set_reset_request
|
Sets the reset request or acknowledge bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
write_clear_reset_request
|
Clears the reset request or acknowledge bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
write_slave_tx_enable
|
Writes to the slave transmit enable bit in the General Configuration and Transmit CPRI Alarms Register (0xE)
|
|
write_pref_hdlc
|
Sets the Preferred HDLC Rate Register (0xA)
|
|
write_pref_protocol
|
Sets the Preferred Protocol Version Register (0x11)
|
|
write_seed
|
Sets the Scrambler Seed Register (0x12)
|
|
write_pref_eth_ptr
|
Sets the Preferred Ethernet Pointer Register (0x8)
|
|
write_fec_error_injection_rate
|
For RS-FEC enabled cores sets the Bit Error Injection Rate in the FEC_Control Register (0x1F)
|
|
write_fec_error_injection_seed
|
For RS-FEC enabled cores sets the Bit Error Injection Seed in the FEC_Control Register (0x1F)
|
In addition, general purpose write and read functions are provided to access other areas of the CPRI management register map.
