AXI4-Lite Management Interface - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

When this option is selected, the core is generated with an AXI4-Lite memory interface. The core management signals are converted to AXI4-Lite signaling by an instance of the AXI4-Lite IPIF core. See Example Design.