The following table shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).
| Vivado IDE Parameter/Value(1) | User Parameter/Value (1) | Default Value |
|---|---|---|
| Master/Slave | Master_Slave | Master |
| Master | Master | |
| Slave | Slave | |
| Speed Selection | Line_Rate | 3.072G_and_under |
| 3.072G and under | 3.072G_and_under | |
| 4.915G and under | 4.915G_and_under | |
| 6.144G and under | 6.144G_and_under | |
| 9.830G and under | 9.830G_and_under | |
| 10.137G and under | 10.137G_and_under | |
| 12.165G and under | 12.165G_and_under | |
| 24.330G and under | 24.330G_and_under | |
| Use 32-bit Datapath | Use_32bit | False |
| Use 64-bit Datapath | Use_64bit | False |
| Reference Clock | Ref_Clk | 122.88 MHz |
| 122.88 MHz | 122.88 MHz | |
| 153.60 MHz | 153.60 MHz | |
| 245.76 MHz | 245.76 MHz | |
| 307.20 MHz | 307.20 MHz | |
| 368.64 MHz | 368.64 MHz | |
| 307.20 MHz / 245.76MHz | 307.20MHz_/_245.76MHz | |
| 307.20MHz / 368.64MHz | 307.20MHz_/_368.64MHz | |
| 307.20MHz / 380.16MHz | 307.20MHz_/_380.16MHz | |
| Free running receive clock | Free_Running_RX_Reference | False |
| Management Clock Rate | Aux_Clk_Rate | 125.0 |
| Free Run Clock Rate | Freerun_Clk_Rate | 7.5 |
| Transceiver location | GT_Location | XnYn |
| CMAC location | CMAC_Location | CMACE4_XnYn |
| Reference clock location | RefClk_Location | refclk0 |
| QPLL Selection | QPLL_Selection | QPLL0 |
| QPLL0 | QPLL0 | |
| QPLL1 | QPLL1 | |
| Additional transceiver control and status ports | TransceiverControl | False |
| GT Type | GT_Type |
GTHE2/GTXE2/GTPE2/ GTHE3/GTYE3/GTHE4/ GTYE4/GTYE5/GTYP |
| Select GT Wizard Type | GT_WIZARD_TYPE | Legacy_GT_Wizard |
| Legacy GT Wizard | Legacy_GT_Wizard | |
| GT Wizard Subsystem | GT_Wizard_Subsystem | |
| Include R-21 Timers | Has_R21_Timers | True |
| AXI4-Lite Management Interface | AXI_ipif | False |
| ORI Support | Use_ORI | False |
| Include Ethernet Logic | Has_Ethernet | True |
| Use GMII Interface | Use_GMII | False |
| Bypass Ethernet FIFOs | Bypass_Buffer | False |
| Shared Logic | SupportLevel | 0 |
| Include Shared Logic in core | 1 | |
| Include Shared Logic in example design | 0 | |
| Real Time Vendor-Specific Support | RT_Vendor_Support | False |
| FEC Enabled Mode | Use_FEC | False |
| Use Hard FEC Receiver | Use_Hard_FEC | False |
| Generate a Hard FEC CPRI Wrapper | Hard_FEC_Wrapper | False |
| Agnostic Line Coding Aware Mode | Agnostic_Mode | False |
| 614.4 Mb/s support | Line_Rate_0_6144 | True |
| 1228.8 Mb/s support | Line_Rate_1_2288 | True |
| 2457.6 Mb/s support | Line_Rate_2_4576 | True |
| 3072.0 Mb/s support | Line_Rate_3_072 | True |
| 4915.2 Mb/s support | Line_Rate_4_9152 | False |
| 6144.0 Mb/s support | Line_Rate_6_144 | False |
| 9830.4 Mb/s support | Line_Rate_9_8304 | False |
| 8110.08 Mb/s support | Line_Rate_8_11008 | False |
| 10137.6 Mb/s support | Line_Rate_10_1376 | False |
| 12165.12 Mb/s support | Line_Rate_12_16512 | False |
| 24330.24 Mb/s support | Line_Rate_24_33024 | False |
| Line Rate Hard FEC | Line_Rate_HFEC | No_Hard_FEC_support |
| 8110.08 Mb/s support | 8110.08_Mb/s_support | |
| 10137.6 Mb/s support | 10137.6_Mb/s_support | |
| 12165.12 Mb/s support | 12165.12_Mb/s_support | |
| 24330.24 Mb/s support | 24330.24_Mb/s_support | |
| No Hard FEC support | No_Hard_FEC_support | |
| Low Line Rate Equalization Mode | Low_Rate_Eq_Mode | Auto |
| Low Line Rate Insertion Loss | Low_Rate_Ins_Loss | 14 |
| High 8b10b Line Rate Equalization Mode | Mid_Rate_Eq_Mode | Auto |
| High 8b10b Line Rate Insertion Loss | Mid_Rate_Ins_Loss | 20 |
| 64b66b Line Rate Equalization Mode | High_Rate_Eq_Mode | Auto |
| 64b66b Line Rate Insertion Loss | High_Rate_Ins_Loss | 25 |
| CDC FIFO depth | CDC_FIFO_Depth | Standard |
|
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