Device, Package, and Speed Grade Selections - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

The CPRI core supporting operation at line rates up to 3,072.0 Mb/s can be implemented in these AMD devices:

  • Zynq 7000 SoCdevices, XC7Z030, and larger, with speed grade of -1 or higher
  • Virtex 7 devices with a speed grade of -1 or higher
  • Kintex 7 devices with a speed grade of -1 or higher
  • Kintex 7 Low Voltage devices with a speed grade of -2L
  • Artix 7 devices with a speed grade of -1 or higher
  • UltraScale architecture with a speed grade of -1 or higher

The CPRI core supporting operation at line rates of up to 4,915.2 Mb/s can be implemented in Artix 7 devices with a speed grade of -2 or -3 in wire bond packages.

The CPRI core supporting operation at line rates up to 6,144.0 Mb/s can be implemented in these AMD devices:

  • Zynq 7000 SoC (XC7Z030 and larger), Virtex 7, and Kintex 7 devices with a speed grade of -1, -2, or -3
  • Kintex 7 Low Voltage devices with a speed grade of -2L
  • Artix 7 devices with a speed grade of -2 or -3 in non wire-bond packages
  • UltraScale architecture with a speed grade of -1 or higher

The CPRI core supporting operation at line rates up to 9,830.4 Mb/s or 10,137.6 Mb/s can be implemented in Virtex 7, Zynq 7000 SoC (XC7Z030 and larger), and Kintex 7 devices with a speed grade of -2 or -3 in FFG packages and in UltraScale architecture with a speed grade of -1 or higher.

The CPRI core supporting operation at line rates up to 12,165.12 Mb/s can be implemented in Virtex 7, Zynq 7000 SoC (XC7Z030 and larger), and Kintex 7 devices with a speed grade of -3 in FFG packages and in UltraScale architecture with a speed grade of -1 or higher.

The CPRI core supporting operation at line rates up to 24,330.24 Mb/s can be implemented in -2 and -3 speed grade UltraScale architecture that use the GTYE3 transceiver. The CPRI core also supports this option for all speed grade UltraScale+ devices using GTYE4 transceivers and Versal adaptive SoC(s) using GTY/GTYP transceivers.