This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.
For AMD Versal™ adaptive SoC(s), the core can be used in Vivado IP integrator or the Vivado Integrated Design Environment flow (RTL flow). However the choice of GT Wizard IP in the CPRI GUI defines the flow used.
When configuring the CPRI core with the Legacy GT Wizard the IP integrator is the only supported flow using Block Automation to generate and configure Versal adaptive SoC Transceiver cores.
When configuring the CPRI core with the GT Wizard subsystem either the IP Integrator or the Vivado Integrated Design Environment flow (RTL flow) can be used.
For AMD UltraScale+™ , AMD UltraScale™ , and 7 series families either IP integrator flow or the Vivado Integrated Design Environment flow can be used to customize and generate the core.
If you are customizing and generating the core in the IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information.
IP integrator might auto-compute certain
configuration values when validating or generating the design. To check whether the values
do change, see the description of the parameter in this chapter. To view the parameter
value, run the validate_bd_design command in the Tcl
console.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
- Either select the IP from the Vivado IP catalog or place the CPRI IP core on the IP integrator canvas, depending on which Vivado flow you are using.
- Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).
The following figure shows the Vivado IDE configuration tab for the CPRI core.