CMAC Location - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

In selected UltraScale+ devices where a Hard FEC is supported the CMAC (Hard FEC) location can be specified with this Vivado IDE option. To guarantee timing closure do not select CMAC and GT locations which cross an SLR boundary. See UltraScale and UltraScale+ FPGAs Packaging and Pinouts (UG575) [Ref 17] and Zynq UltraScale+ Device Packaging and Pinouts (UG1075) [Ref 18] for details.