In selected UltraScale+ devices where a Hard FEC is supported the CMAC (Hard FEC) location can be specified with this Vivado IDE option. To guarantee timing closure do not select CMAC and GT locations which cross an SLR boundary. See UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) and Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075) for details.