The following figure shows the clock configuration for a CPRI core on a Virtex 7, Zynq 7000 SoC, and Kintex 7 device supporting 10,137.6 Mb/s operation. In master mode, the reference clock is generated from a crystal oscillator. In slave mode the reference is generated from the recovered clock by an external jitter-removal PLL.
The quad PLL is used at 9,830.4 and 10,137.6 Mb/s.
At 9,830.4 Mb/s, the quad PLL provides a 4,915.2 MHz clock to the transceiver. At 10,137.6
Mb/s, the quad PLL provides a 5,068.8 MHz clock to the transceiver. This is input to the
transceiver through the QPLLCLK input. At line rates of 6144.0
Mb/s and lower the CPLL is used.
The transmitter clock for the transceiver channel
block is provided through the clk_316_in port of the IP core.
This runs at 316.8 MHz when operating at 10,137.6 Mb/s. The clock for the IP core logic,
provided to the clk_in input of the core, runs at 307.2 MHz.
The difference in clock frequencies allows for correct operation using the 64B/66B encoding
system.
When running at lower rates with the 8B/10B
encoding system, clk_316, and clk_in run at the same rate, from 245.76 MHz when operating at 9,830.4 Mb/s down
to 15.36 MHz when operating at 614.4 Mb/s.
The recovered clock is routed to the CPRI core by
a BUFR in Virtex 7 devices and by a BUFH in Kintex 7, and Zynq 7000 SoC devices. A BUFG is required on the TXOUTCLK output of the transceiver on Kintex 7 and Zynq 7000 SoC devices only.
In slave cores, rather than routing the recovered clock directly to the external jitter-removal PLL as shown in the preceding figure, the recovered clock can be prescaled within the FPGA to a constant nominal rate of 15.36 MHz for all line rates. The example design supplied with the core contains an example implementation of this prescaling technique.