Management Register Map - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

The memory map for the management register block is shown in the following table.

Table 1. Management Register Addresses
Address AXI Address Name Mode
0x0 0x0 Status Code and Alarm Register (0x0) Read Only
0x1 0x4 Miscellaneous Status Register (0x1) Read Only
0x2 0x8 Current HDLC Rate Register (0x2) Read Only
0x3 0xC Current Ethernet Pointer Register (0x3) Read Only
0x4 0x10 Received Subchannel 2, Word 0 Register (0x4) Read Only
0x5 0x14 Received Subchannel 2, Word 1 Register (0x5) Read Only
0x6 0x18 Received Subchannel 2, Word 2 Register (0x6) Read Only
0x7 0x1C Received Subchannel 2, Word 3 Register (0x7) Read Only
0x8 0x20 Transceiver Loopback and Ethernet Reset Request Register (0x8) Read/Write
0x9 0x24 Transceiver Barrel Shift Position Register(0x9) Read Only
0xA 0x28 Preferred HDLC Rate Register (0xA) Read/Write
0xB 0x2C Preferred Ethernet Pointer Register (0xB) Read/Write
0xC 0x30 Current Line Speed Register (0xC) Read Only
0xD 0x34 Line Speed Capability Register (0xD) Read/Write
0xE 0x38 General Configuration and Transmit CPRI Alarms Register (0xE) Read/Write
0xF 0x3C R21 Timers Register (0xF) Read Only
0x10(1) 0x40 Current Protocol Version Register (0x10) Read Only
0x11(1) 0x44 Preferred Protocol Version Register (0x11) Read/Write
0x12(1) 0x48 Scrambler Seed Register (0x12) Read/Write
0x13(1) 0x4C Descrambler Seed Register (0x13) Read Only
0x14(2) 0x50 Transmit FIFO Transit Time Register (0x14) Read Only
0x15 0x54 Watchdog Timeout Value Register (0x15) Read/Write
0x16(3) 0x58 Gearbox Latency Register (0x16) Read Only
0x17 0x5C FIFO Fill Level Register (0x17) Read/Write
0x18 0x60 General Debug Register (0x18) Read Only
0x19 0x64 High Resolution FIFO Transit Time—Integer Part Register (0x19) Read Only
0x1A 0x68 High Resolution FIFO Transit Time—Fractional Part Register (0x1A) Read Only
0x1B(4) 0x6C FEC Status Register (0x1B) Read Only
0x1C(4) 0x70 FEC CW Count Register (0x1C) Read Only
0x1D(4) 0x74 FEC Corrected CW Count Register (0x1D) Read Only
0x1E(4) 0x78 FEC Uncorrected CW Count Register (0x1E) Read Only
0x1F (4) 0x7C FEC Control Register (0x1F) Read/Write
0x20(5) 0x80 Hard FEC Variable Latency Register (0x20) Read Only
  1. Present only in cores that support operation at 4,915.2 Mb/s or higher.
  2. Present only in Kintex 7, Virtex 7 and Zynq 7000 SoC-based cores supporting 10,137.6 or 12,165.12 Mb/s.
  3. Present only in UltraScale-based cores supporting line rates up to 10,137.6, 12,165.12, or 24,330.24 Mb/s.
  4. Present only in UltraScale-based cores supporting line rates up to 24,330.24Mb/s with FEC Enabled mode.
  5. Present only in UltraScale+ based cores supporting Hard FEC Enabled mode.