Transceiver Barrel Shift Position Register(0x9) - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English
Table 1. Transceiver Barrel Shift Position Register
Bits Description
31:7 Reserved
6:0 Current position of the transceiver receive barrel shifter. See R21 Calculation for more details.

In cores operating at 8b10b line rates, the current transceiver barrel shift position is reported using this register.