When the design is implemented on UltraScale architecture a free running clock is required to drive the transceiver reset circuitry. This clock should run at a slower speed than the system clock at the lowest supported line rate. In the example design XDC file this clock is constrained to the speed of the system clock at 614.4 Mb/s.
When a 32-bit datapath is selected:
create_clock -name reset_block_clk -period 65.104 [get_ports gtwiz_reset_clk_freerun_in]
When 16-bit datapath is selected:
create_clock -name reset_block_clk -period 32.552 [get_ports gtwiz_reset_clk_freerun_in]