Because the UTRA-FDD I/Q Module accepts a basic frame of I/Q sample data broadside into the core when tx_iq_enable is asserted and then serializes it according to the configured I/Q channel count and data widths, it is very difficult to describe the latency from any given bit in any given I/Q sample for any given configuration of channels in the core, either in the transmit or receive direction.
Instead, the latency between the tx_iq_enable signal assertion and the first bit of word 0 of the basic frame is given; from this reference, it is possible to work out the delay of any given bit in the basic frame thereafter.
The transmit delay for the multiplexed I/Q data interface is shown in This Figure . The figure shows the I/Q data basic frame being captured into the core by the iq_tx_enable signal and the first bit of word 0 of the basic frame being transmitted on the output of the transceiver. T tx is the delay between those two events.
The overall delay (T tx ) is made up of the contributions listed in Table: Contributions to Transmit Delay, GTYE3 Transceiver , but with 1 extra cycle of latency.
Similarly, the latency between the reception of the first bit of word 0 in the basic frame to the assertion of iq_rx_data_valid is given; the latency of any given bit in the received basic frame is offset from this reference value.
The receive delay using the UTRA-FDD I/Q Module is shown in This Figure . The figure shows the first encoded bit of word 0 of the basic frame being received at the transceiver pins and the basic frame data being qualified as valid on the iq_rx_i and iq_rx_q outputs by the iq_rx_data_valid signal. T rx is the delay between those two events.
The overall delay Trx is made up of the contributions listed in Table: Contributions to Receive Delay GTYE3 Transceiver , plus 1 Tc.
Where T c is the length of a basic frame:
T c = 1/f c = 1/3.84 MHz = 260.416667 ns
Where f c is the chip rate (f c = 3.84 MHz)