Transceiver Interfaces (Versal ACAP Cores Only)

Transceiver Interfaces (Versal ACAP Cores Only) - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID

PG056

Release Date

2022-11-16

Version

8.11 English

Table: Versal GT TX IP Interface Ports shows the Versal GT TX Interface ports.

Table 3-29: Versal GT TX IP Interface Ports
Port	Direction	Clock Domain	Description
ch_txctrl0[15:0]	Out	System Clock	TX disparity control to the Versal ACAP transceiver.
ch_txctrl1[15:0]	Out	System Clock	TX disparity polarity control to the Versal ACAP transceiver.
ch_txctrl2[7:0]	Out	System Clock	TX char is K to the Versal ACAP transceiver.
ch_txdata[127:0]	Out	System Clock	TX data to the Versal ACAP transceiver.
ch_txdiffctrl[4:0]	Out	Async	TX diffctrl to the Versal ACAP transceiver.
ch_txheader[5:0]	Out	System Clock	TX header to the Versal ACAP transceiver.
ch_txinhibit	Out	System Clock	TX inhibit to the Versal ACAP transceiver. Blocks transmission of TX data.
ch_txlatclk	Out	N/A	TX asynchronous gearbox latency clock to the Versal ACAP transceiver. Driven by hires_clk if R21 timers option is selected in CPRI GUI.
ch_txmstdatapathreset	Out	System Clock	TX master data path reset sequence start to the Versal ACAP transceiver.
ch_txmstreset	Out	System Clock	TX master reset sequence start to the Versal ACAP transceiver.
ch_txmstresetdone	In	System Clock	TX master reset sequence done from the Versal ACAP transceiver.
ch_txphdlypd	Out	Async	TX phase and delay alignment circuit power down to the Versal ACAP transceiver.
ch_txphdlyreset	Out	Async	TX phase alignment reset to the Versal ACAP transceiver.
ch_txphdlyresetdone	In	Async	TX phase alignment reset done from the Versal ACAP transceiver.
ch_txpmaresetdone	In	Async	TX PMA reset done from the Versal ACAP transceiver.
ch_txpolarity	Out	System Clock	TX polarity control to the Versal ACAP transceiver. Currently not used.
ch_txpostcursor[4:0]	Out	Async	Transmitter post-cursor TX pre-emphasis control to the Versal ACAP transceiver. Currently not used.
ch_txprbssel[3:0]	Out	System Clock	TX PRBS generator test pattern control to the Versal ACAP transceiver. Currently not used.
ch_txprecursor[4:0]	Out	Async	Transmitter pre-cursor TX pre-emphasis control to the Versal ACAP transceiver. Currently not used.
ch_txrate[7:0]	Out	System Clock	TX line rate control to the Versal ACAP transceiver.
ch_txsequence[6:0]	Out	System Clock	TX sequence counter to the Versal ACAP transceiver.
ch_txsyncallin	Out	Async	TX phase alignment sync in to the Versal ACAP transceiver. For multi-lane auto mode, currently not used.
ch_txsyncdone	In	Async	TX phase alignment complete from the Versal ACAP transceiver.
ch_txuserrdy	Out	System Clock	TX user clocks stable to the Versal ACAP transceiver.
Notes: 1. CPRI only uses the above subset of the available signals on the Versal ACAP Transceiver Tx_GT_IP_Interface. For further details, see the Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331) [Ref 21] . 2. The ports in Table: Versal GT TX IP Interface Ports are connected between the CPRI core and the Versal ACAP Transceiver using Block Automation, see Block Automation (Versal ACAP Only) for details.

Table: Versal GT RX IP Interface Ports shows the Versal GT RX Interface ports.

Table 3-30: Versal GT RX IP Interface Ports
Port	Direction	Clock Domain	Description
ch_rxctrl0[15:0]	In	Recovered Clock	RX char is K from the Versal ACAP transceiver.
ch_rxctrl1[15:0]	In	Recovered Clock	RX disparity error from the Versal ACAP transceiver.
ch_rxctrl2[7:0]	In	Recovered Clock	RX char is comma from the Versal ACAP transceiver.
ch_rxctrl3[7:0]	In	Recovered Clock	RX not in table error from the Versal ACAP transceiver.
ch_rxdata[127:0]	In	Recovered Clock	RX data from the Versal ACAP transceiver.
ch_rxdatavalid[1:0]	In	Recovered Clock	RX data valid from the Versal ACAP transceiver.
ch_rxgearboxslip	Out	Recovered Clock	RX Gearbox Slip to the Versal ACAP transceiver.
ch_rxheader[5:0]	In	Recovered Clock	RX Header from the Versal ACAP transceiver.
ch_rxheadervalid[1:0]	In	Recovered Clock	RX Header Valid from the Versal ACAP transceiver.
ch_rxlatclk	Out	N/A	RX asynchronous gearbox latency clock to the Versal ACAP transceiver. Driven by hires_clk if R21 timers option is selected in CPRI GUI.
ch_rxlpmen	Out	Async	RX LPM mode enable to the Versal ACAP transceiver.
ch_rxmstdatapathreset	Out	Recovered Clock	RX master data path reset sequence start to the Versal ACAP transceiver.
ch_rxmstreset	Out	Recovered Clock	RX master reset sequence start to the Versal ACAP transceiver.
ch_rxmstresetdone	In	Recovered Clock	RX master reset sequence done from the Versal ACAP transceiver.
ch_rxphdlypd	Out	Async	Rx phase and delay alignment circuit power down to the Versal ACAP transceiver.
ch_rxphdlyreset	Out	Async	RX phase alignment reset to the Versal ACAP transceiver.
ch_rxphdlyresetdone	In	Async	RX phase alignment reset done from the Versal ACAP transceiver.
ch_rxpmaresetdone	In	Async	RX PMA reset done from the Versal ACAP transceiver.
ch_rxpolarity	Out	Recovered Clock	RX polarity control to the Versal ACAP transceiver. Currently not used.
ch_rxprbscntreset	Out	Recovered Clock	RX PRBS error count reset to the Versal ACAP transceiver.
ch_rxprbssel[3:0]	Out	Recovered Clock	RX PRBS generator test pattern control to the Versal ACAP transceiver. Currently not used.
ch_rxrate[7:0]	Out	Recovered Clock	RX line rate control to the Versal ACAP transceiver.
ch_rxresetdone	In	Recovered Clock	RX reset complete from the Versal ACAP transceiver.
ch_rxsyncallin	Out	Async	RX phase alignment sync in to the Versal ACAP transceiver. For multi-lane auto mode, currently not used.
ch_rxsyncdone	In	Async	RX phase alignment complete from the Versal ACAP transceiver.
ch_rxuserrdy	Out	Recovered Clock	RX user clocks stable to the Versal ACAP transceiver.
Notes: 1. CPRI only uses the above subset of the available signals on the Versal ACAP Transceiver Rx_GT_IP_Interface. For further details the Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331) [Ref 21] . 2. The ports in Table: Versal GT RX IP Interface Ports are connected between the CPRI core and the Versal ACAP Transceiver using Block Automation, see Block Automation (Versal ACAP Only) for details.