General Configuration and Transmit CPRI Alarms Register (0xE) - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English
Table 2-14: General Configuration and Transmit CPRI Alarms Register

Bits

Default
Value

Description

31

0

Software reset

When set to 1 the core performs a reset. The bit reads back a 1 while reset is in progress and 0 when complete. The reset is considered complete when clk_ok is asserted. The software reset does not affect the other management register settings.

clk_ok remains Low until a valid line rate is selected by the core. Setting the line speed capability register to 0 does not disable the management interface.

30:29

N/A

Reserved

28

1

GMII mode

If the GMII interface is selected and this field is set to 1 then 8-bit GMII data is transferred over the GMII interface. If this field is set to 0 4-bit MII data is transferred.

27:24

5

Ethernet Jam Byte Count

If Ethernet Receiver Ignores TX_EN is FALSE, this field defines the number of bytes the core asserts the eth_rx_er signal on the Ethernet interface. Valid values: 1 to 15.

23:20

12

Ethernet Gap Byte Count

If the Ethernet Gap in C&M Channel bit (bit 17) is set to 1, this field defines the number of bytes of Interframe Gap. The valid range is 3 to 15. This functionality is not supported when the GMII interface is selected.

19

1

Ethernet Transmitter Ignores RX_DV

When set to 0, the core asserts eth_col if eth_tx_en is asserted at the same time as eth_rx_dv. When set to 1, eth_col does not depend on the state of eth_rx_dv.

18

1

Ethernet Receiver Ignores TX_EN

When set to 0, the core does not attempt to source a frame on the Ethernet receive interface if a transmission is in progress (true half-duplex). When set to 1, the receiver ignores the transmitter and sources a frame on the receive interface if one is available.

17

1

Ethernet Gap in C&M Channel

When set to 1, the core inserts Ethernet interpacket gaps across the CPRI fast C&M channel. When set to 0, the core does not insert interpacket gaps on the CPRI Fast C&M channel but sends frames as fast as they are supplied on the Ethernet interface.

16

1

HDLC Rate Adaptation

When set to 1, the enable for the transmit data and the valid signals for the receive data are pulsed High at regular intervals. This maintains the average HDLC data rate negotiated at start-up. When set to 0, the core outputs enable and valid signals that frame a burst of HDLC data. The length of the burst is dependent on the HDLC rate negotiated at start-up.

15

0

Sync Header Reversal

When set to 1 the txheader(1:0) and rxheader(1:0) bits are reversed if 64B66B encoding is enabled.

14:9

N/A

Reserved

8

0

Slave Transmit Enable

When the Slave Transmit Enable bit is set to 0, the slave does not turn on its transmitted output until HFNSYNC is achieved. When set to 1, the slave does turn on its transmitted output immediately on start-up. This bit is read when the design enters the L1 synchronization state.

7:3

N/A

Reserved

2

0

SAP Defect Indicator (SDI)

1

N/A

Reserved

0

Reset (Downlink—Request, Uplink—Acknowledge)

When this bit is set to 1 on a core configured as a Master, a 1 is transmitted in the reset bit of control word Z.130.0 of the outbound CPRI frame. When the Reset bit is then set to 0, the core continues to transmit a 1 for the Z.130.0 reset bit for 10 Hyperframes and then reverts to transmitting 0.

When the core is configured as a slave, setting this bit to 1 causes the Reset bit in Z.130.0 to be asserted as reset acknowledge . After a 0 is written the core transmits a 1 for the Z.130.0 Reset bit for 5 Hyperframes and then reverts to transmitting 0.

Other than obeying the requirements specified previously for performing two writes on the management interface (that is, wait for mgmnt_ack and then deassert mgmnt_req signal for at least one clock cycle before starting a subsequent write) there is no delay requirement between writing 1 and writing 0 to the Reset bit, bit 0.

See section 4.2.7.6.1 of CPRI Specification 7.0 [Ref 1] for more information.