Ethernet Clock Domain - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

When the bypass Ethernet Buffers option is not selected, the Ethernet clock domain is present. In the example design XDC the Ethernet clock is constrained to be 125 MHz in GMII mode and 25 MHz in MII mode.

When the MII interface option is selected:

create_clock -name eth_ref_clk -period 40.000 [get_ports eth_ref_clk]

When the GMII interface option is selected:

create_clock -name eth_ref_clk -period 8.000 [get_ports eth_ref_clk]