Hard RS-FEC Receiver - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
Release Date
8.11 English

In UltraScale+ devices supporting the 100G Ethernet RS-FEC Hard block, a Hard FEC option can be selected when using a fixed line rate of either 24,330.24, 12,165.12, 10,137.6, or 8,110.08 Mb/s.

The hard RS-FEC block is used only in the RX data path while the soft RS-FEC sub-IP described in the above section is used in the TX data path. Up to four CPRI IP lanes can be connected to the Hard RS-FEC receiver. All four CPRI lanes must run at the same line rate. Line speed negotiation is not currently available in Hard FEC implementations. This architecture gives a sizable saving in resources in the RX data path when more than one CPRI lane is used. There is no resource saving in the TX data path, therefore it is not provided.

If the CPRI core is configured with shared logic in the core, three interfaces are provided for external CPRI cores to connect to the Hard RS-FEC block. If the CPRI core is configured with shared logic in the example design, a single interface is provided to connect to the host CPRI core which has the Hard RS-FEC block. The Hard FEC Interface is described in the Hard RS-FEC Interface section. An example of the Hard FEC sharing is shown in This Figure . The Hard RS-FEC block is designed in accordance with CPRI Specification v7.0 , October 9, 2015 [Ref 1] section 6.9.

When using Hard FEC mode, the codeword alignment process can take as long as 3.3 ms to complete L1 synchronization.