• UltraScale architecture, Zynq-7000 SoC, Virtex-7, and Kintex-7 devices : The additional delay is five datapath clock cycles, or 100 UI.
• Artix-7 devices : The additional delay is five datapath clock cycles plus two RECCLK cycles, or 240 UI.
• UltraScale architecture, Zynq-7000 SoC, Virtex-7, and Kintex-7 devices : The additional delay is five datapath clock cycles, or 100 UI.
• Artix-7 devices : The additional delay is five datapath clock cycles plus two RECCLK cycles, or 240 UI.