The static configuration interface is made up of a small number of ports that must be statically wired to indicate to the core how the transceiver that it is connected to is configured and where it is sited. The core uses this information to determine which DRP registers need to be manipulated in the transceiver and clock management primitives. These ports are described in the following table.
Port | Direction | Clock Domain | Description |
---|---|---|---|
use_pll | In | Management Clock | (Zynq 7000 SoCs, Virtex 7, Kintex 7, and
Artix 7 devices only) When generating the core clock a PLLE2 can be used as a replacement for the MMCME2. See Using the PLL to Generate the Core Clock for details of the additional wrapper changes that must be applied. 0 - core uses a MMCME2 1 - core uses a PLLE2 |
pll_select | In | Management Clock | (Artix 7 devices only) Provides support on programming either PLL0 or PLL1 in the GTPE2_COMMON block. 00 - Reserved 01 - Core uses PLL0 10 - Core uses PLL1 11 - Core uses PLL0 on the transmit path and PLL1 on the receive path. See Free Running Receiver Reference Clock (Artix 7 Only). |
qpll_select | In | Management Clock | (UltraScale architecture only) Specifies which QPLL to use on cores supporting 8,110.08, 9,830.4, 10,137.6, 12,165.12, or 24,330.24 Mb/s. 0 - QPLL0 is used 1 - QPLL1 is used |
These signals should not be dynamically driven but be wired to the appropriate constant values before implementation.