Disabling the Core - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

Setting the speed capability register to all 0s disables the core and the transceiver tile. This permits configuration registers such as the Ethernet pointer or HDLC rate values to be safely set before re-enabling the core.

Setting soft reset in the management register interface has a higher priority than disabling the speed capability register.