Licensing and Ordering - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID: PG056
Release Date: 2022-11-16
Version: 8.11 English

CPRI v8.11 LogiCORE IP Product Guide
IP Facts
Introduction
Features
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
Applications
System Requirements
Recommended Design Experience
Licensing and Ordering
License Checkers
License Type
Product Specification
Chip Period (T C ) in This Document
Related Information
Performance
Maximum Frequencies
Resource Utilization
Speed Grade Support
CPRI Core Structure
For Versal ACAPs
For UltraScale and 7 Series Devices
Block Layer
Core Support Layer (UltraScale and 7 Series Devices Only)
Port Descriptions
Management Register Map
Status Code and Alarm Register (0x0)
Miscellaneous Status Register (0x1)
Current HDLC Rate Register (0x2)
Current Ethernet Pointer Register (0x3)
Received Subchannel 2, Word 0 Register (0x4)
Received Subchannel 2, Word 1 Register (0x5)
Received Subchannel 2, Word 2 Register (0x6)
Received Subchannel 2, Word 3 Register (0x7)
Transceiver Loopback and Ethernet Reset Request Register (0x8)
Transceiver Barrel Shift Position Register(0x9)
Preferred HDLC Rate Register (0xA)
Preferred Ethernet Pointer Register (0xB)
Current Line Speed Register (0xC)
Line Speed Capability Register (0xD)
General Configuration and Transmit CPRI Alarms Register (0xE)
R21 Timers Register (0xF)
Current Protocol Version Register (0x10)
Preferred Protocol Version Register (0x11)
Scrambler Seed Register (0x12)
Descrambler Seed Register (0x13)
Transmit FIFO Transit Time Register (0x14)
Watchdog Timeout Value Register (0x15)
Gearbox Latency Register (0x16)
FIFO Fill Level Register (0x17)
General Debug Register (0x18)
High Resolution FIFO Transit Time—Integer Part Register (0x19)
High Resolution FIFO Transit Time—Fractional Part Register (0x1A)
FEC Status Register (0x1B)
FEC CW Count Register (0x1C)
FEC Corrected CW Count Register (0x1D)
FEC Uncorrected CW Count Register (0x1E)
FEC Control Register (0x1F)
Hard FEC Variable Latency Register (0x20)
Designing with the Core
General Design Guidelines
Use the Example Design as a Starting Point
Know the Degree of Difficulty
Keep It Registered
Recognize Timing Critical Signals
Use Supported Design Flows
Make Only Allowed Modifications
Clocking and Resets
Versal ACAP Cores
UltraScale and 7 Series Cores
Interfacing to the Core
Data Interfaces
I/Q Interface
UTRA-FDD I/Q Module
E-UTRA I/Q Module
Legacy Raw I/Q Module
Vendor-Specific Data Interface
Real Time Vendor-Specific Support
Frame and Synchronization Interface
HDLC Interface
Ethernet Interface
MII Interface
GMII Interface
Bandwidth Timing on the MII Interface
Connecting the CPRI core to an Ethernet MAC on the FPGA
Interface with Ethernet Frame Buffers Bypassed
ORI Module
Structure Agnostic Interface
Line Rate Switching
8B10B Scrambling
Serial Interface
Transceiver Interfaces (Versal ACAP Cores Only)
Transceiver Status and Control Interface (Versal ACAP Cores Only)
Transceiver Interface (UltraScale and 7 Series Cores Only)
Transceiver Debug Interface
Transceiver Data Monitor Interface
Management Interface
AXI4-Lite Memory Mapped Interface
Status and Alarm Interfaces
Static Configuration Interface
Dynamic Configuration Interface
Hard RS-FEC Interface
Hard FEC Wrapper IP Core Interface
Design Considerations
Reference Clock Selection
Clock Configuration
Virtex-7, Zynq-7000 SoC, and Kintex-7 Devices
Supporting Line Rates up to 3,072.0 Mb/s
Supporting Line Rates up to 6,144.0 Mb/s
Supporting Line Rates up to 9,830.4 Mb/s
Supporting Line Rates up to 10,137.6 Mb/s
Supporting Line Rates up to 12,165.12 Mb/s
Artix-7 Devices
Supporting Line Rates up to 3,072.0 Mb/s
Supporting Line Rates up to 6,144.0 Mb/s
UltraScale Architecture
Supporting Line Rates up to 3,072.0 Mb/s and 6,144 Mb/s
Supporting Line Rates up to 9,830.4 Mb/s
Supporting Line Rates up to 10,137.6 Mb/s and 12,165.12 Mb/s
Supporting Line Rates up to 24,330.24 Mb/s
UltraScale GTYE3-based Devices (368.64 MHz Reference Clock)
UltraScale GTYE3-based and UltraScale+ GTYE4-based Devices (245.76 MHz Reference Clock)
Versal ACAP Architecture
Supporting Line Rates Up to 24,330.24 Mb/s
Free Running Receiver Reference Clock (Artix-7 Only)
Using the PLL to Generate the Core Clock
Resource Sharing
Transmitter Clock Sharing
Transceiver Common Block Sharing
Hard FEC Block Sharing
Core Support Layer
<component_name>_clocking.vhd
<component_name>_tx_alignment.vhd
<component_name>_gt_common.vhd
<component_name>_resets.vhd
Line Speed Configuration and Negotiation
Single Speed Operation
Multi-speed Operation with Rate Negotiation
Disabling the Core
RS-FEC Enabled Mode
Hard RS-FEC Receiver
Hard FEC Wrapper IP
Using an External GMII Interface
Receive CDC FIFO
CPRI Master Cores
CPRI Slave Cores
Delay Measurement and Requirement 21 (R21)
Delay Model
Delay Through the GTXE2 Transceiver
Delay Through the GTHE2 Transceiver
Delay Through the GTPE2 Transceiver
Delay Through the GTHE3 Transceiver
Delay Through the GTYE3 Transceiver
Additional Line Rate Delay
Example:
Delay Through the GTHE4 Transceiver
Delay Through the GTYE4 Transceiver
Delay Through the Versal ACAP GTY Transceiver
Additional Line Rate Delay
Example
Delay Across the CDC FIFO
Receive CDC FIFO
Transmit CDC FIFO
Overall Delay
Core I/Q Interface
UTRA-FDD I/Q Module
R21 Calculation
Coarse Delay Measurement
Additional Pipeline Delays
Cores Supporting 3,072.0 Mb/s
Cores Supporting 4,915.2/6,144.0 Mb/s
Cores Supporting 9,830.4 Mb/s
Cores Supporting 10,137.6/12,165.12 Mb/s
Cores Supporting 12,165.12 Mb/s and Above
Cores Supporting FEC Enabled Mode
Cores Supporting Hard FEC Enabled Mode
Hard FEC Wrapper IP Cores
Performing the Cable Delay Calculation
Calculating T 14 (CPRI Master)
Calculating T offset (CPRI Slave)
Calculating the Cable Delay
Example R21 Delay Calculation
R21A Calculation
R19 Calculation
Design Flow Steps
Customizing and Generating the Core
Component Name
Master/Slave
Speed and Reference Clock Selection
Use 32-bit Datapath
Use 64-bit Datapath
Free Running Receive Clock
Management Clock Rate
Free Run Clock Rate
Transceiver Settings
Transceiver Location
CMAC Location
Reference Clock Location
QPLL Selection
GT Type
Additional Transceiver Control and Status Ports
Optional Features
Include R21 Timers
AXI4-Lite Management Interface
ORI Support
Include Ethernet Logic
Use GMII Interface
Bypass Ethernet FIFOs
Real Time Vendor-Specific Support
FEC Enabled Mode
Use Hard FEC Receiver
Structure Agnostic Interface
Line Rate Support
Line Rate Hard FEC
Shared Logic
Hard FEC Wrapper
Advanced
Transceiver Equalization Mode and Insertion Loss Settings
User Parameters
Block Automation (Versal ACAP Only)
Connecting to Transceivers Using Block Automation for Versal ACAPs
Block Automation Output
Output Generation
Versal ACAP Architecture-Based Cores
UltraScale and 7 Series Architecture-Based Cores
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies and Clock Management
System Clock Domain
Recovered Clock Domain
Management Clock Domain
Reset Block Clock Domain
Ethernet Clock Domain
Hi-Speed Clock Domain
Hard FEC Constraints
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Versal ACAP-Based Designs
UltraScale and 7 Series-Based Designs
Hard FEC Wrapper Example Design
Test Bench
Verification, Compliance, and Interoperability
Simulation
Hardware Testing
Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Device Migration
Port Changes in Version 8.11
Port Changes in Version 8.10
Port Changes in Version 8.9
Port Changes in Version 8.8
Port Changes in Version 8.7
Port Changes in Version 8.6
Port Changes in Version 8.5
Port Changes in Version 8.4
Ports Added in Version 8.3
Ports Added in Version 8.2
Ports Added in Version 8.1
Ports Added in Version 8.0
Changed Ports in Version 8.0
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Vivado Design Suite Debug Feature
Hardware Debug
Hardware Demonstration Design
General Checks
CPRI Specific Checks
AXI4-Lite Interface Debug
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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