In certain circumstances it might be preferable to use a free running reference clock to clock the receiver PLL in the GTPE2 transceiver of the CPRI slave core. This removes the need for the external jitter-removal PLL to be free-running in the absence of a reference signal.
When the free_running_rx_reference generic is set to TRUE, both
PLL0 and PLL1 in the GTPE2 transceiver are used. The receive
datapath uses PLL1. This PLL is clocked from
a crystal oscillator. The transmit datapath uses PLL0. This is clocked from the recovered clock through an
external jitter removal PLL. This PLL need not be free running in the
absence of the reference clock from the GTPE2. The pll_select input to the core should be tied to 11 in this
mode.
The following figure shows the clocking for a system supporting 6,144.0 Mb/s.