ORI Module - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID

PG056

Release Date

2022-11-16

Version

8.11 English

The ORI module provides an interface between ORI specific control ports and the vendor-specific interface. The ORI specific information is carried in the control words of subchannels 50, 51, and 52 of the CPRI frame.

IMPORTANT: The 614.4 Mb/s line rate is not available when ORI is selected.

Table 3-24: ORI Subchannel Allocation
Subchannel Index (Ns)	Allocation
52	PORT ID
50 and 51	Received Total Wideband Power (RTWP) measurement report

In the transmit direction the ORI module takes data from ports holding the PORT ID and RTWP information and maps it into subchannels 50 to 52 of the CPRI frame using the vendor-specific interface. In the receive direction the data received in subchannels 50 to 52 is extracted and output on the PORT ID and RTWP ports. The ports of the ORI module are described in Table: ORI Module Signals - Core Interface and Table: ORI Module Signals - ORI Specific Interface . All signals are synchronous to clk .

Table 3-25: ORI Module Signals - Core Interface
Port	Direction	Clock Domain	Description
iq_tx_enable	In	System Clock	Transmit enable indicating the start of a new basic frame.
nodebfn_tx_strobe	In	System Clock	UMTS Node B frame strobe in transmit direction
basic_frame_first_word	In	System Clock	Indicates the start of a new basic frame
nodebfn_rx_strobe	In	System Clock	UMTS Node B frame strobe in receive direction
vendor_tx_data	Out	System Clock	Vendor-specific data for transmit direction.
vendor_tx_ns	In	System Clock	Subchannel Index
vendor_tx_xs	In	System Clock	Control Word Index
vendor_rx_data	In	System Clock	Vendor-specific data for receive direction.
vendor_rx_ns	In	System Clock	Subchannel Index
vendor_rx_xs	In	System Clock	Control Word Index

Table 3-26: ORI Module Signals - ORI Specific Interface
Port	Direction	Clock Domain	Description
tx_mac_address[47:0]	In	System Clock	Ethernet MAC address of the ORI node
tx _port_number[7:0]	In	System Clock	Port number of the ORI node
rx_mac_address[47:0]	Out	System Clock	Received Ethernet MAC address from the link partner
rx_port_number[7:0]	Out	System Clock	Received port number from the link partner
tx_rtwp_group_n[15:0] (n = 1 to 20,40 or 64)	In	System Clock	Slave cores only. Up to 20 (3 Gb/s cores), 40 (6 Gb/s cores) or 64 (10 Gb/s cores) AxC RTWP groups for transmission from RE
rx_rtwp_group_n[15:0] (n = 1 to 20,40 or 64)	Out	System Clock	Master cores only. Up to 20 (3 Gb/s cores), 40 (6 Gb/s cores) or 64 (10 Gb/s cores) AxC RTWP groups received from RE
ori_tx_en	Out	System Clock	Signal indicating that ORI data is being sent during the current basic frame
ori_rx_valid_strobe	Out	System Clock	Signal indicating that the data on the ORI receiver output is valid

The ORI interface transmitter routes the values on the tx_mac_address and tx_port_number ports to the vendor_tx_data port when the core is transmitting subchannel 52. This is shown in This Figure . Similarly the RTWP information on the tx_rtwp_group_n ports is routed through during the transmission of subchannels 50 and 51. The information is mapped to vendor_tx_data for transmission.

Figure 3-64: ORI Transmit Timing
X-Ref Target - Figure 3-64

The ORI interface receiver samples vendor_rx_data during subchannels 50 to 52 and outputs the recovered values on the rx_mac_address and rx_port_number ports as shown in This Figure . Similarly the RTWP information is extracted from the incoming data and output on the rx_rtwp_group_n ports.

Figure 3-65: ORI Receive Timing
X-Ref Target - Figure 3-65

A nodebfn_rx_strobe from the CPRI core is required before the RTWP information is output. The RTWP information is only updated in hyperframes 0, 30, 60, 90 and 120. The strobe is required to collect the data from the correct hyperframe.