Block Automation Output - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

The following example shows the result of running Block Automation. The Versal ACAP Transceiver GT Quad will be created with the correct settings required for the selected CPRI IP core(s). The CPRI IP core(s) will be connected to the Versal ACAP Transceiver GT Quad.

The remaining unconnected ports, such as ref_clock , core_clk , encommaalign , resets, etc., need to be connected manually. For an example of how to connect the remaining ports, generate the CPRI IP example design (see Example Design ) in Vivado and use this as a reference.

This Figure shows the result of running Block Automation on two CPRI IP cores with default settings.

Figure 5-8: Block Automation Example on Two CPRI IP Cores

X-Ref Target - Figure 5-8