Verilog in VHDL - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

Vivado synthesis has the following limitations when instantiating a Verilog module in a VHDL design unit:

  • Use explicit port association. Specify formal and effective port names in the port map.
  • All parameters are passed at instantiation, even if they are unchanged.
  • The parameter override is named and not ordered. The parameter override occurs through instantiation, and not through defpas.
  • Only component instantiation is supported when instantiating a Verilog module in VHDL. Direct entity instantiation is not supported.