Generics in Packages - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

VHDL-2008 supports putting a generic in a package and being able to override that generic when the package is declared. For example:

package my_pack is
generic(
length : integer);

subtype my_type is std_logic_vector(length-1 downto 0);
end package my_pack;

This declares a subtype of std_logic_vector but does not specify the length. The calling VHDL file specifies what the length should be when the package is instantiated:

library ieee;
use leee.std_logic_1164.all;

package my_pack1 is new work.my_pack generic map (length => 5);
package my_pack2 is new work.my_pack generic map (length => 3);
use work.my_pack1.all;
use work.my_pack2.all;

library ieee;
use ieee.std_logic_1164.all;

entity test is port (
clk : in std_logic;
in1 : in work.my_pack1.my_type;
in2 : in work.my_pack2.my_type;
out1 : out work.my_pack1.my_type;
out2 : out work.my_pack2.my_type);
end test;

This code uses the same package to declare two different subtypes and be able to use them.