Behavioral Verilog Module Declaration Example Two - 2024.2 English

Behavioral Verilog Module Declaration Example Two - 2024.2 English - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2024-11-13

Version

2024.2 English

module example ( input A, inputB, output O
);

assign O = A & B;
endmodule