Arrays Example Two - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

This coding example describes an array of 64 8-bit wide elements. These elements can be assigned only in structural Verilog code.

wire [7:0] mem_array [63:0];