KEEP_HIERARCHY Verilog Example - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

On Module

(* keep_hierarchy = "yes" *) module bottom (in1, in2, in3, in4, out1, out2);

On Instance

(* keep_hierarchy = "yes" *)bottom u0 (.in1(in1), .in2(in2), .out1(temp1));