Procedural Assignments - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English
  • Behavioral Verilog procedural assignments:
    • Assign values to variables declared as reg.
    • Are introduced by always blocks, tasks, and functions.
    • Model registers and Finite State Machine (FSM) components.
  • Vivado synthesis supports:
    • Combinatorial functions
    • Combinatorial and sequential tasks
    • Combinatorial and sequential always blocks