Vivado synthesis allows the conversion of gated clocks. To perform this conversion, use:
- A switch in the Vivado IDE that instructs the tool to attempt the conversion.
- The
GATED_CLOCK
RTL attribute or XDC property that instructs the tool about which signal in the gated logic is the clock.
Place this attribute on the signal or port that is the clock. To control the switch:
- Select Tools > Settings > Project Settings > Synthesis.
- In the Options area, set the
-gated_clock_conversion
option to one of the following values:- off
- Disables the gated clock conversion.
- on
- Gated clock conversion occurs if the
gated_clock
attribute is set in the RTL code. This option gives you more control of the outcome.
- auto
- Gated clock conversion occurs if either of the following
events are true:
- The
gated_clock
attribute is set toYES
. - The Vivado synthesis can detect the gate and there is a valid clock constraint set. This option lets the tool make decisions.
- The
CAUTION:
Care should be taken when using
attributes like KEEP_HIERARCHY, DONT_TOUCH, and MARK_DEBUG. These attributes can
interfere with gated clock conversion if placed on hierarchies or instances that need to
change to support the conversion.