Vivado synthesis supports VHDL design entities and configurations except as noted in the following table.
VHDL Construct | Support Status |
---|---|
VHDL Entity Headers | |
Generics | Supported |
Ports | Supported, including unconstrained ports |
Entity Statement Part | Unsupported |
VHDL Packages | Supported |
VHDL Physical Types | |
TIME | Supported, but only in functions for constant calculations. |
REAL | Supported, but only in functions for constant calculations. |
VHDL Modes | |
Linkage | Unsupported |
VHDL Declarations | |
Type |
Supported for the following:
|
VHDL Objects | |
Constant Declaration | Supported except for deferred constant |
Signal Declaration | Supported except for register and bus type signals. |
Attribute Declaration | Supported for some attributes, otherwise skipped. |
VHDL Specifications | |
HIGHLOW | upported |
LEFT | Supported |
RIGHT | Supported |
RANGE | Supported |
REVERSE_RANGE | Supported |
LENGTH | Supported |
POS | Supported |
ASCENDING | Supported |
Configuration |
Supported only with the all clause for instances list. • If no clause is added, Vivado synthesis looks for the entity or architecture compiled in the default library. |
Disconnection | Unsupported |
Underscores | Object names can contain underscores in general (DATA_1), but Vivado synthesis does not allow signal names with leading underscores ( _DATA_1). |
VHDL Operators | |
Logical Operators: and, or, nand, nor, xor, xnor, not | Supported |
Relational Operators: =, /=, <, <=, >, >= | Supported |
& (concatenation) | Supported |
Adding Operators: +, - | Supported |
* | Supported |
/ | Supported if the right operand is a constant power of 2, or if both operands are constant. |
Rem | Supported if the right operand is a constant power of 2. |
Mod | Supported if the right operand is a constant power of 2. |
Shift Operators: sll, srl, sla, sra, rol, ror | Supported |
Abs | Supported |
** | Supported if the left operand is 2. |
Sign: +, - | Supported |
VHDL Operands | |
Abstract Literals | Only integer literals are supported. |
Physical Literals | Ignored |
Enumeration Literals | Supported |
String Literals | Supported |
Bit String Literals | Supported |
Record Aggregates | Supported |
Array Aggregates | Supported |
Function Call | Supported |
Qualified Expressions | Supported for accepted predefined attributes. |
Types Conversions | Supported |
Allocators | Unsupported |
Static Expressions | Supported |
Wait Statement | |
Wait on sensitivity_list until boolean_expression . |
Supported with one signal in the sensitivity list and in the boolean expression. Multiple wait statements are not supported. wait statements for Latch descriptions are not supported. |
Wait for time_expression . |
Unsupported |
Assertion Statement | Supported for static conditions only. |
Signal Assignment Statement |
Supported. Delay is ignored. |
Variable Assignment Statement | Supported |
Procedure Call Statement | Supported |
If Statement | Supported |
Case Statement | Supported |
Loop Statements | |
Next Statements | Supported |
Exit Statements | Supported |
Return Statements | Supported |
Null Statements | Supported |
Concurrent Statements | |
Process Statement | Supported |
Concurrent Procedure Call | Supported |
Concurrent Assertion Statements | Ignored |
Concurrent Signal Assignments |
Supported, except after clause, transport or guarded options, or waveforms. UNAFFECTED is supported. |
Component Instantiation Statements | Supported |
for-generate | Statement supported for constant bounds only |
if-generate | Statement supported for static condition only |