Memory Inference Capabilities - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

Memory inference capabilities include the following:

  • Support for any size and data width. Vivado synthesis maps the memory description to one or several RAM primitives
  • Single-port, simple-dual port, true dual port
  • Up to two write ports
  • Multiple read ports

Provided that only one write port is described, Vivado synthesis can identify RAM descriptions with two or more read ports that access the RAM contents at addresses different from the write address.

  • Write enable
  • RAM enable (block RAM)
  • Data output reset (block RAM)
  • Optional output register (block RAM)
  • Byte write enable (block RAM)
  • Each RAM port can be controlled by its distinct clock, port enable, write enable, and data output reset
  • Initial contents specification
  • Vivado synthesis can use parity bits as regular data bits to accommodate the described data widths
Note: For more information on parity bits see the user guide for the device you are targeting.