Instantiating VHDL in Verilog - 2024.2 English - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2024-11-13
Version
2024.2 English

To instantiate a VHDL design unit in a Verilog design, do the following:

  1. Declare a module name with the same as name as the VHDL entity that you want to instantiate (optionally followed by an architecture name).
  2. Perform a normal Verilog instantiation.