Multi-Dimensional Array Example One - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

This coding example describes an array of 256 x 16 wire elements of 8 bits each. These elements can be assigned only in structural Verilog code.

wire [7:0] array2 [0:255][0:15];