Setting Constraints - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2024-06-28
Version
2024.1 English

The following table shows the supported Tcl commands for Vivado timing constraints. The commands are linked to more information to the full description in the Vivado Design Suite Tcl Command Reference Guide (UG835).

Table 1. Supported Synthesis Tcl Commands
Command Type Commands  
Timing Constraints create_clock create_generated_clock set_false_path set_input_delay
set_output_delay set_max_delay set_multicycle_path get_cells
set_clock_latency set_clock_groups set_disable_timing get_ports
Object Access all_clocks all_inputs all_outputs  
get_clocks get_nets get_pins  

For details on these commands, see the following documents:

  • Vivado Design Suite Tcl Command Reference Guide (UG835)
  • Vivado Design Suite User Guide: Using Constraints (UG903)
  • Vivado Design Suite Tutorial: Using Constraints (UG945)
  • Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)