PARALLEL_CASE (Verilog Only) - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2024.1 English

PARALLEL_CASE specifies that the case statement must be built as a parallel structure. Logic is not created for an if -elsif structure. Because this attribute affects the compiler and the logical behavior of the design, it can be set in the RTL only.

(* parallel_case *) case select
3'b100 : sig = val1;
3'b010 : sig = val2;
3'b001 : sig = val3;
Note: This attribute can only be controlled through the Verilog RTL.