Example of for-generate Statement (VHDL) - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
Release Date
2023.2 English

Filename: for-generate.vhd

In this coding example, the for-generate statement describes the calculation of the result and carries out for each bit position of this 8-bit adder.

-- A for-generate example
-- for_generate.vhd
entity for_generate is
A, B : in BIT_VECTOR(0 to 7);
CIN : in BIT;
SUM : out BIT_VECTOR(0 to 7);
COUT : out BIT
end for_generate;

architecture archi of for_generate is
signal C : BIT_VECTOR(0 to 8);
C(0) <= CIN;
COUT <= C(8);
LOOP_ADD : for I in 0 to 7 generate
SUM(I) <= A(I) xor B(I) xor C(I);
C(I + 1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));
end generate;
end archi;