Describing a Clock Enable After the Wait Statement Example (VHDL) - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

You can describe the clock enable separately, as follows:

process begin
wait until rising_edge(clk);
if clken = '1' then
q <= d;
end if;
end process;