Advantages of VHDL - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English
  • Enforces stricter rules, in particular strongly typed, less permissive and error-prone
  • Initialization of RAM components in the HDL source code is easier (Verilog initial blocks are less convenient)
  • Package support
  • Custom types
  • Enumerated types
  • No reg versus wire confusion