Multi-Dimensional Array Example Two - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

This coding example describes an array of 256 x 8 register elements, each 64-bits wide. These elements can be assigned in behavioral Verilog code.

reg [63:0] regarray2 [255:0][7:0];