Variable Part Selects Verilog Coding Example - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2024-12-11
Version
2024.2 English
reg [3:0] data;
reg [3:0] select; // a value from 0 to 7
wire [7:0] byte = data[select +: 8];