Flip-Flops and Registers Reporting - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2023.2 English
  • Registers are inferred and reported during HDL synthesis.
  • The number of Registers inferred during HDL synthesis might not precisely equal the number of Flip-Flop primitives in the Design Summary section.
  • The number of Flip-Flop primitives depends on the following processes:
    • Absorption of Registers into DSP blocks or block RAM components
    • Register duplication
    • Removal of constant or equivalent Flip-Flops